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Publications
   
 
Summary Paper

Please cite our summary paper when you publish results that you have obtained with PARSEC:

Benchmarking Modern Multiprocessors [ BIBTEX ]
Christian Bienia. Ph.D. Thesis. Princeton University, January 2011.
[ PDF ]     [ PS ]

 

More Publications about PARSEC

In addition to our summary paper we have also published the following papers about PARSEC:

Fidelity and Scaling of the PARSEC Benchmark Inputs [ BIBTEX ]
Christian Bienia and Kai Li. In Proceedings of the IEEE International Symposium on Workload Characterization, December 2010.
[ PDF ]     [ PS ]

Characteristics of Workloads Using the Pipeline Programming Model [ BIBTEX ]
Christian Bienia and Kai Li. In Proceedings of the 3rd Workshop on Emerging Applications and Many-core Architecture, June 2010.
[ PDF ]     [ PS ]

PARSEC 2.0: A New Benchmark Suite for Chip-Multiprocessors [ BIBTEX ]
Christian Bienia and Kai Li. In Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation, June 2009.
[ PDF ]     [ PS ]

PARSEC vs. SPLASH-2: A Quantitative Comparison of Two Multithreaded Benchmark Suites on Chip-Multiprocessors [ BIBTEX ]
Christian Bienia, Sanjeev Kumar and Kai Li. In Proceedings of the IEEE International Symposium on Workload Characterization, September 2008.
[ PDF ]     [ PS ]

The PARSEC Benchmark Suite: Characterization and Architectural Implications [ BIBTEX ]
Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh and Kai Li. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, October 2008.
[ PDF ]     [ PS ]

 

Other Publications about PARSEC

Other research groups have published the papers listed below about PARSEC. If you know of any other publications about PARSEC please let us know so we can add them to this list.

Statistical Performance Comparisons of Computers[ BIBTEX ]
Tianshi Chen, Qi Guo, Olivier Temam, Yue Wu, Yungang Bao, Zhiwei Xu, and Yunji Chen. In IEEE Transactions on Computers (IEEE TC) , 2014.
[ PDF ]     [Related Link: Hierarchical Performance Testing (HPT)]

Optimized Hardware for Suboptimal Software: The Case for SIMD-aware Benchmarks[ BIBTEX ]
Juan M. Cebrian, Magnus Jahre, Lasse Natvig. In Proceedings of 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) , March 2014.
[ PDF ]     [Related Link: ParVec homepage]

Thread Reinforcer: Dynamically Determining Number of Threads via OS Level Monitoring[ BIBTEX ]
Kishore Kumar Pusukuri, Rajiv Gupta, Laxmi N. Bhuyan. In Proceedings of the 2011 International Symposium on Workload Characterization, October 2011.
[ PDF ]

A Communication Characterization of SPLASH-2 and PARSEC[ BIBTEX ]
Nick Barrow-Williams, Christian Fensch and Simon Moore. In Proceedings of the 2009 International Symposium on Workload Characterization, October 2009.
[ PDF ]

Understanding PARSEC Performance on Contemporary CMPs[ BIBTEX ]
Major Bhadauria, Vincent M. Weaver and Sally A. McKee. In Proceedings of the 2009 International Symposium on Workload Characterization, October 2009.
[ PDF ]

Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors [ BIBTEX ]
Abhishek Bhattacharjee and Margaret Martonosi. In Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques, October 2009.
[ PDF ]

Characterizing and Improving the Performance of Intel Threading Building Blocks[ BIBTEX ]
Gilberto Contreras and Margaret Martonosi. In Proceedings of the IEEE International Symposium on Workload Characterization, September 2008.
[ PDF ]

 


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